This thesis discusses the design and implementation of a VHDL generator for Wallace tree with (3:2) counter modules and (2:2) counter modules to solve fast addition problem. This absence has severely constrained basic research environments, and has precipitated the current sub-optimal nature of CAD in VHDL tool development. (IF) for the exchange of VHDL encoded electronic data among CAD systems. National Research Council Canada - National Science Library Standard Analyzer of VHDL Applications for Next Generation Technology (SAVANT)

This idea itself is not new, and the C to VHDL compiler combines the best approaches from existing solutions developed over many previous years, with the introduction of some new unique improvements. C to VHDL compiler project attempts to remedy that by creating an application, that derives initial VHDL description of a digital system (for further compilation and synthesis), from purely algorithmic description in C programming language. Although very effective and expressive in hands of hardware development specialists, these languages require specific knowledge and experience, unreachable for most scientists and software programmers. Current industry standard in development of digital systems on FPGA platform is based on HDLs. All this makes the FPGA platform very attractive for those looking for efficient heterogeneous, computing environment. FPGA platform offers unique ability to configure the hardware to implement virtually any dedicated architecture, and modern devices provide sufficient number of hardware resources to implement parallel execution platforms with complex processing units. The main goal of C to VHDL compiler project is to make FPGA platform more accessible for scientists and software developers.

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